DocumentCode :
2101819
Title :
An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers
Author :
Thompson, Ross ; Stine, James E.
Author_Institution :
Air Force Research Laboratory, 525 Brooks Road, Rome, NY 13441 USA
fYear :
2015
fDate :
27-29 July 2015
Firstpage :
62
Lastpage :
63
Abstract :
This paper discusses an optimized double-precision floating-point multiplier that can handle both denormalized and normalized IEEE 754 floating-point numbers. Discussions of the optimizations are given and compared versus similar implementations, however, the main objective is keeping compliant for denormalized IEEE 754 floating-point numbers while still maintaining high performance operations for normalized numbers.
Keywords :
Adders; Algorithm design and analysis; Computer architecture; Delays; Economic indicators; Optimization; Standards;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-specific Systems, Architectures and Processors (ASAP), 2015 IEEE 26th International Conference on
Conference_Location :
Toronto, ON, Canada
Type :
conf
DOI :
10.1109/ASAP.2015.7245706
Filename :
7245706
Link To Document :
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