Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs

Power consumption has become the biggest challenge in industry for chip design. We will present that by using small reprogrammable embedded FPGAs (eFPGA) coupled with a processor we can achieve power and energy reduction with a very small silicon overhead. Enhancement of computational power helps lowering down frequency (dynamic frequency scaling) to decrease dynamic power. By having same computational power at lower frequency can help fabricate chip in LP (low power) process compared to GP (general purpose) which helps to significantly reduce static power which is very crucial issue at and below 90 nm technologies. Use of reconfigurable accelerator (eFPGA) raises the natural question of its programming complexity, HW/SW partitioning and silicon overhead. We will present that silicon overhead of eFPGA is small compared to the benefits which can be obtained with it. We will present our profiling tool and Catapulttrade ESL tool of Mentor Graphicsreg to analyze the issue of programming complexity.