Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths

This paper introduces a reconfigurable computing cell architecture for pipelined and systolic datapaths in the mixed grained reconfigurable coprocessor array system (MiGCop). The cell is efficiently capable of building scalable parallel-parallel, serial-parallel, and serial-serial signed multipliers. Several cells can be combined to form a reconfigurable coprocessor that is tightly coupled with clusters of specially-designed lightweight RISC processors. In this paper, we present two different cell structures and compare their implementations using the 0.13 mum standard cell CMOS technology from Faraday^reg and select the design with the most efficient area-delay product for the emerging MiGCop system. We will show that the cells are capable of computation frequencies higher than 250 MHz at a reasonable power consumption.