Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip

The design of 3D circuits have been motivated by the need of decreasing the wire length in System-on-Chip (SoC) composed of more and more high number of processing elements. In general, advantages such as aiding the test methodology and increasing fault tolerance can be observed. However, the development of 3D circuits is not trivial, and there are still challenges in the manufacture process. The objective of this work is to address a low cost solution to improve the yield in TSVs, combining fault tolerance in horizontal interconnections, in order to minimize the fault susceptibility in 3D-NoCs. Comparisons among different serialization levels have been developed to show the advantages.