High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit

This paper presents a hardware design for the Fractional Motion Estimation (FME) Interpolation Unit compatible with the High Efficiency Video Coding (HEVC) standard. The proposed architecture was designed to consider fixed 16×16 Prediction Unit (PU) size in order to drastically reduce the computational effort. This decision was made taking into account several evaluations, using the HEVC Reference Software, to find out the number of occurrences of each PU size and their coding efficiency impact. The designed architecture was described in VHDL and synthesized to an Altera Stratix III FPGA. The results show that the designed architecture is able to process QFHD videos at 60 frames per second with a 353.8 MHz clock frequency.