A timing optimization technique for nanoscale CMOS circuits susceptible to process variations

Performance variation is one of the primary concerns in nanoscale CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware, Transistor (PVT) sizing algorithm is proposed, which is capable of reducing worst-case delay, delay uncertainty, and delay sensitivity to process variations in nanoscale CMOS circuits. The proposed algorithm is based on identifying the significance of timing paths in a design, and performing respective optimization for optimal design performance. Additional advantages in this algorithm include its simplicity, accuracy, independent of the transistor order, and initial sizing factors. Using 90 nm CMOS process, the proposed algorithm has demonstrated an average improvement in worst-case delay by 36.9%, delay uncertainty by 44.1%, delay sensitivity by 19.8%, and power-delay-product by 35.3% when compared to their initial performances.