DocumentCode
2102298
Title
Celator: A Multi-algorithm Cryptographic Co-processor
Author
Fronte, Daniele ; Perez, Annie ; Payrat, Eric
Author_Institution
IM2NP, Aix-Marseille Univ., Marseille
fYear
2008
fDate
3-5 Dec. 2008
Firstpage
438
Lastpage
443
Abstract
Nowadays hi-tech secure products offer more services and more security. The corresponding market is now oriented towards more flexibility. As an answer we propose here a multi-algorithm cryptographic co-processor called Celator. A main processor entrusts to the Celator the cryptographic tasks like encrypting or decrypting data blocks using secret key encryption algorithms such as advanced encryption standard (AES) or data encryption standard (DES). Moreover Celator allows hashing data using the secure hash algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator corresponds to their flexible hardware implementation. Moreover an user can (under specific conditions) implement its own cryptographic algorithm in Celator. Celator can perform an AES encryption with a throughput of 47 Mbps, the DES encryption with a throughput of 26 Mbps, condense a 512 bit SHA message with a throughput of 36 Mbps. Finally we report performance comparisons among Celator, general purpose processors, and some dedicated and dynamically reconfigurable circuits.
Keywords
microprocessor chips; private key cryptography; Celator; advanced encryption standard; bit rate 26 Mbit/s; bit rate 36 Mbit/s; bit rate 47 Mbit/s; data block decryption; data block encryption; data encryption standard; hardware mode; multialgorithm cryptographic co-processor; secret key encryption algorithms; secure hash algorithms; software mode; Circuits; Coprocessors; Cryptography; Data security; Field programmable gate arrays; Hardware; Helium; Information processing; Software algorithms; Throughput; AES; Communication system security; Cryptography; Smart cards; Systolic Processors; key cryptography;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGAs, 2008. ReConFig '08. International Conference on
Conference_Location
Cancun
Print_ISBN
978-1-4244-3748-1
Electronic_ISBN
978-0-7695-3474-9
Type
conf
DOI
10.1109/ReConFig.2008.76
Filename
4731834
Link To Document