The multi 2D systolic design and implementation of Convolutional Neural Networks

A novel Systolic Convolutional Neural Network (SCoNN) architecture suitable to be implemented in a single hardware die is proposed in this paper. A large size of memory is required to store the input and intermediate data resulted among convolutional layers in the CoNN. However, to parallelize the computations, multiple memory accesses should be achieved simultaneously. Consequently, memory bandwidth should be increased by the use of either fast expensive components or complicated managed interleaved scheme. Our proposed system can address this challenge efficiently. This is achieved due to the use of smaller memory to store the input pattern and to re-use it as an intermediate memory for inter-processing patterns that produced between two convolutional layers. Using systolic technique which can efficiently exploit its input leads to achieve this goal. A high parallelism level can be achieved with a minimal number of memory accesses. Also, the proposed computational units is designed to be suitable for processing an image of scaled resolutions. The reason behind that is attributed to using a sliding window architecture to implement the convolution process. Now apart from the size of the input pattern or window and instead of feeding the window across the image, the image is fed through the window due to using FIFO caching scheme. According to these advantages, an easily, efficient, and scalable SCoNN architecture can be implemented using small FPGA resources.