Title :
Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness
Author :
Ker, Ming-Dou ; Hsu, Hsin-Chyh ; Peng, Jeng-Jie
Author_Institution :
Nanoelectronics & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Taiwan
Abstract :
A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 μm/0.5 μm has been successfully improved from the original 450 V to become 675 V in a 0.25 μm CMOS process.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; integrated circuit technology; 0.25 micron; 0.5 micron; 300 micron; 675 V; CMOS ICs; ESD current discharge; ESD implantation method; electrostatic discharge robustness; gate-grounded NMOS device; machine-model ESD robustness improvement; sub-quarter-micron CMOS processes; CMOS integrated circuits; CMOS process; CMOS technology; Current measurement; Electrostatic discharge; Integrated circuit modeling; MOS devices; Robustness; Semiconductor device modeling; Stress;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the
Print_ISBN :
0-7803-7416-9
DOI :
10.1109/IPFA.2002.1025614
