Title :
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
Author :
Lin, I-Cheng ; Huang, Chih-Yao ; Chao, Chuan-Jane ; Ker, Ming-Dou ; Chuan, Sung-Yu ; Leu, Len-Yi ; Chiu, Fu-Chien ; Tseng, Jen-Chou
Author_Institution :
Technol. Dev. Div., Winbond Electron. Corp., Hsinchu, Taiwan
Abstract :
Latchup failure induced by ESD protection circuits occurred in a high-voltage IC product. Latchup occurred anomalously at only several output pins. All output pins have nearly identical layouts except the side output pin has a N-well resistor of RC gate-coupled PMOS beside. It was later found this N-well resistor is the main cause of inducing latchup.
Keywords :
CMOS integrated circuits; electrical faults; electrostatic discharge; integrated circuit reliability; power integrated circuits; protection; HV CMOS IC product; HVIC; RC gate-coupled PMOS; anomalous latchup failure; device reliability; electrostatic discharge; high-voltage IC; n-well resistor; on-chip ESD protection circuit; Breakdown voltage; CMOS integrated circuits; Circuit testing; Clamps; Electrostatic discharge; Pins; Power supplies; Protection; Resistors; Thyristors;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the
Print_ISBN :
0-7803-7416-9
DOI :
10.1109/IPFA.2002.1025615
