A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS

Measurement results of an analog channel decoder in 65nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)₈ convolutional codes and takes 0.104 mm² on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3μW the decoder performs the required computations to provide 1dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.