Title :
Device optimization for digital sub-threshold operation
Author :
Paul, Bipul C. ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In this paper, we provide optimized transistor structures for digital sub-threshold circuit operation for ultra-low power applications. Results show that at 500 MHz operation, an inverter chain implemented using optimized transistors consumes as low as 2 times less power than circuits using standard transistors and operated in sub-threshold.
Keywords :
circuit optimisation; digital integrated circuits; integrated circuit design; logic design; logic gates; low-power electronics; 500 MHz; device optimization; digital sub-threshold circuit operation; inverter chain; optimized transistor structures; power consumption; ultra-low power applications; Capacitance; Circuit simulation; Doping profiles; Energy consumption; Frequency; Inverters; Leakage current; Medical simulation; Power dissipation; Threshold voltage;
Conference_Titel :
Device Research Conference, 2004. 62nd DRC. Conference Digest [Includes 'Late News Papers' volume]
Print_ISBN :
0-7803-8284-6
DOI :
10.1109/DRC.2004.1367809
