Building-in reliability, application to bipolar/CMOS/DMOS technology

Author

Gagnard, X. ; Bonnaud, O.

Author_Institution

Groupe de Microelectronique et Visualisation UPRESA 6076, Rennes I Univ., France

fYear

2002

fDate

2002

Firstpage

147

Lastpage

151

Abstract

A permanent goal for an integrated circuit foundry is the improvement of reliability to avoid failures during component life. Ideally, the components should be tested in the mission profile conditions for the total duration. Specific tests must be accelerated to reduce the measurement time without creating new degradations, but also to detect the true defect or its origins. We have developed a building-in reliability approach for a front-end. The wafer level reliability (WLR) is set-up by electrical or physical tests during or at the end of the process, to eliminate defects directly at their origins. Our study concerned mainly a bipolar/CMOS/DMOS (BCD) technology.

Keywords

BIMOS integrated circuits; fault location; integrated circuit design; integrated circuit reliability; integrated circuit testing; life testing; production testing; BCD technology; accelerated tests; bipolar/CMOS/DMOS technology; building-in reliability; component life failures; component tests; defect detection; defect elimination; electrical tests; front-end; integrated circuit foundry; measurement time; mission profile conditions; physical tests; reliability; wafer level reliability; Acceleration; CMOS technology; Circuit testing; Electric breakdown; Fabrication; Integrated circuit measurements; Integrated circuit reliability; Life estimation; Oxidation; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2002. IPFA 2002. Proceedings of the 9th International Symposium on the

Print_ISBN

0-7803-7416-9

Type

conf

DOI

10.1109/IPFA.2002.1025635

Filename

1025635