Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM´s). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (V_th) exactly (precise L´s) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (V_bs) for having a single L_opt for all transistors (as opposed to having two different L_opt, one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although V_th and L change by ~10%, by using V_bs we can still achieve very high SNM´s, while additionally reducing power and energy to ~50%.