Title :
A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications
Author :
Ramchan Woo ; Sungdae Choi ; Ju-Ho Sohn ; Seong-Jun Song ; Young-Don Bae ; Chi-Weon Yoon ; Byeong-Gyu Nam ; Jeong-Ho Woo ; Sung-Eun Kim ; In-Cheol Park ; Sungwon Shin ; Kyung-Dong Yoo ; Jin-Yong Chung ; Hoi-Jun Yoo
Author_Institution :
KAIST, Daejeon, South Korea
Abstract :
A 121 mm/sup 2/ graphics LSI is for portable 2D/3D graphics and MPEG4 applications. The LSI contains a RISC processor with MAC, a 3D rendering engine, 29Mb DRAM and is built in a 0.16/spl mu/m pure DRAM technology. Programmable clocking allows the LSI to operate in several power modes for various applications. In lower cost mode, power consumption is under 210mW, delivering 264M texture mapped pixels per second.
Keywords :
computer graphic equipment; large scale integration; mobile computing; multimedia computing; pipeline processing; rendering (computer graphics); 0.16 micron; 210 mW; 29 Mbit; 3D rendering engine; MPEG4 applications; RISC processor; full 3D pipeline; graphics LSI; mobile multimedia applications; portable 2D/3D graphics; power modes; texture mapped pixels; Clocks; Costs; Engines; Graphics; Large scale integration; MPEG 4 Standard; Pipelines; Random access memory; Reduced instruction set computing; Rendering (computer graphics);
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234200
