Title :
Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications
Author :
Yamauchi, Hiroyuki ; Okada, Shogo ; Taketa, Koji ; Ohyama, Takaharu ; Matsuda, Yuuki ; Mori, Takayoshi ; Okada, Shogo ; Watanabe, Toshio ; Matsuo, Yoshikazu ; Yamada, Y. ; Ichikawa ; Matsushita, Yuki
Author_Institution :
Sanyo Electr. Co. Ltd., Gifu, Japan
Abstract :
A one-chip image processor for next-generation digital cameras and broadband PDA multimedia mobile phones is described. It is capable of processing JPEG2000 data with 30 frames/s and a 27 MHz operating frequency. The process is fabricated in 0.25 /spl mu/m CMOS and contains 8.5M transistors in a 103 mm/sup 2/ area.
Keywords :
CCD image sensors; CMOS digital integrated circuits; digital signal processing chips; discrete wavelet transforms; image coding; multimedia communication; parallel architectures; pipeline processing; 0.25 micron; 0.25/spl mu/m CMOS; 2-pixel parallel pipeline architecture; 27 MHz; CCD image processor; DWT calculation; JPEG2000 data processing; JPEG2000 encoder; block-noise-free JPEG2000 compression; broadband PDA multimedia mobile phones; next-generation digital cameras; one-chip image processor; operating frequency; Costs; Digital cameras; Discrete wavelet transforms; Image coding; Parallel processing; Pipelines; Signal processing; Tiles; Transform coding; Wavelet transforms;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234201
