A 51.2 GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 4-way VLIW processing elements

Author

Kyo, S. ; Koga, T. ; Okazaki, S. ; Uchida, R. ; Yoshimoto, S. ; Kuroda, I.

Author_Institution

NEC Corp., Kawasaki, Japan

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

48

Abstract

A 51.2 GOPS fully programmable and scalable video recognition processor is based on a linear connection of 128 4-way VLIW processing elements and an asynchronous data mapping mechanism. Execution is under 33 ms/frame for complex weather, robust road area/lane marking, and vehicle detection. The chip contains 32.7M transistors in 121 mm/sup 2/ area fabricated in 0.18 /spl mu/m 7M CMOS.

Keywords

CMOS digital integrated circuits; automated highways; automotive electronics; digital signal processing chips; image recognition; intelligent control; parallel architectures; reduced instruction set computing; video signal processing; 0.18 /spl mu/m 7M CMOS; 0.18 micron; 4-way VLIW processing elements; 51.2 GOPS scalable video recognition processor; RISC control processor; asynchronous data mapping mechanism; complex weather; fully programmable video recognition processor; intelligent cruise control; intelligent transport system; linear array; robust road area/lane marking; vehicle detection; Broadcasting; Clocks; Control systems; Decoding; Intelligent control; National electric code; Read-write memory; Reduced instruction set computing; Strontium; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234202

Filename

1234202