A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

Author

Borgatti, M. ; Call, L. ; De Sandre, G. ; Foret, B. ; Iezzi, D. ; Lertora, F. ; Muzzi, G. ; Pasotti, M. ; Poles, M. ; Rolandi, P.L.

Author_Institution

STMicroelectronics, Agrate Brianza, Italy

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

50

Abstract

A 1 GOPS dynamically reconfigurable processing unit with embedded flash memory and SRAM-based FPGA for image/voice processing/recognition applications is described. Code, data and FPGA bitstreams are stored in the embedded flash memory and are independently accessible through 3 content-specific, 64 b I/O ports with a peak read rate of 1.2 GB/s. The system is implemented in a 0.18 /spl mu/m 2P 6M CMOS flash technology with a chip area of 70 mm/sup 2/.

Keywords

CMOS digital integrated circuits; digital signal processing chips; embedded systems; face recognition; field programmable gate arrays; flash memories; reconfigurable architectures; speech recognition; 0.18 micron; 1 GOPS reconfigurable signal processing IC; 1.2 GB/s; 2P 6M CMOS flash technology; 3-port 1.2 GB/s flash memory subsystem; 64 bit; FPGA bitstreams; SRAM-based FPGA; chip area; content-specific 64 b I/O ports; embedded FPGA; embedded flash memory; facial recognition; image/voice processing; image/voice recognition; peak read rate; speech recognition; Aggregates; Field programmable gate arrays; Flash memory; Logic circuits; Microprocessors; Programmable control; Programmable logic arrays; Programmable logic devices; Reconfigurable logic; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234203

Filename

1234203