Title :
Distributed arithmetic architecture of Discrete Wavelet Transform (DWT) with hybrid method
Author :
Ja´afar, Noor Huda ; Ahmad, Ayaz ; Amira, Abbes
Author_Institution :
VLSI Archit. & Syst. Design Res. Lab., Univ. Tun Hussein Onn Malaysia, Batu Pahat, Malaysia
Abstract :
This paper presents the design and implementation of distributed arithmetic (DA) architectures of three-dimensional (3-D) Discrete Wavelet Transform (DWT) with hybrid method for medical image compression. Due to the separability property of the multi-dimensional Haar and Daubechies, the proposed architecture has been implemented using a cascade of three N-point one-dimensional (1-D) Haar/Daubechies and two transpose memories for a 3-D volume of N×N×N, suitable for 3-D medical imaging applications. The architectures were synthesised using VHDL and G-code and implemented on field programmable gate array (FPGA) single board RIO (sbRIO-9632) with Spartan-3 (XC3S2000). Experimental results and an analysis of the area, power consumption, maximum frequency, latency, throughput as well as the subjective test are discussed in this paper.
Keywords :
Haar transforms; data compression; discrete wavelet transforms; distributed arithmetic; field programmable gate arrays; hardware description languages; image coding; medical image processing; 3D discrete wavelet transform; Daubechies transform; FPGA; G-code; Spartan-3 XC3S2000; VHDL; distributed arithmetic architecture; field programmable gate array; hybrid method; medical image compression; multidimensional Haar transform; single board RIO; Biomedical imaging; Discrete wavelet transforms; Field programmable gate arrays; Table lookup;
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location :
Abu Dhabi
DOI :
10.1109/ICECS.2013.6815463