• DocumentCode
    2104306
  • Title

    MetaCore: an application specific DSP development system

  • Author

    Yang, Jin-Hyuk ; Kim, Byoung-Woon ; Nam, Sang-Jun ; Cho, Jang-Ho ; Seo, Sang-Won ; Ryu, Chang-Ho ; Kwon, Young-Su ; Lee, Dae-Hyun ; Lee, Jong-Yeol ; Kim, Jong-Sun ; Yoon, Hyun-Dhong ; Kim, Jae-Yeol ; Lee, Kun-Moo ; Hwang, Chan-Soo ; Kim, In-Hyung ; Kim, J

  • Author_Institution
    Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
  • fYear
    1998
  • fDate
    19-19 June 1998
  • Firstpage
    800
  • Lastpage
    803
  • Abstract
    This paper describes the MetaCore system which is an ASIP (Application-Specific Instruction set Processor) development system targeted for DSP applications. The goal of MetaCore system is to offer an efficient design methodology meeting specifications given as a combination of performance, cost and design turnaround time. MetaCore system consists of two major design stages: design exploration and design generation. In the design exploration stage, MetaCore system accepts a set of benchmark programs and a formal specification of ISA (Instruction Set Architecture), and estimates the hardware cost and performance for each hardware configuration being explored. Once a hardware configuration is chosen, the system helps generate a VLSI processor design in the form of HDL along with the application program development tools such as C compiler, assembler and instruction set simulator.
  • Keywords
    application specific integrated circuits; development systems; digital signal processing chips; high level synthesis; Application-Specific Instruction set Processor; DSP applications; HDL; ISA; MetaCore system; VLSI processor design; application program development tools; design exploration; design generation; development system; formal specification; hardware configuration; Application specific processors; Costs; Design methodology; Digital signal processing; Formal specifications; Hardware design languages; Instruction sets; Process design; Program processors; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1998. Proceedings
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-89791-964-5
  • Type

    conf

  • Filename
    724580