Title :
A dual channel /spl Sigma//spl Delta/ ADC with 40MHz aggregate signal bandwidth
Author :
Tabatabaei, A. ; Onodera, K. ; Zargari, M. ; Samavati, H. ; Su, D.K.
Author_Institution :
Atheros Commun., Sunnyvale, CA, USA
Abstract :
A dual-channel /spl Sigma//spl Delta/ ADC has been integrated in 0.13/spl mu/m CMOS technology with an oversampling ratio of 4. The ADC employs a cascade of low-pass and band-pass modulators and achieves an aggregate quadrature signal bandwidth of 40MHz at a sampling frequency of 160MS/s and 54dB dynamic range while dissipating 175mW from a 2.5V supply.
Keywords :
CMOS integrated circuits; sigma-delta modulation; 0.13 micron; 175 mW; 2.5 V; 40 MHz; CMOS technology; band-pass modulator; dual-channel sigma-delta ADC; dynamic range; low-pass modulator; oversampling ratio; quadrature signal bandwidth; Aggregates; Bandwidth; CMOS technology; Clocks; Energy consumption; Frequency; Multi-stage noise shaping; Noise shaping; Quantization; Sampling methods;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234210
