Title :
A 10Gb/s/ch 50mW 120/spl times/130/spl mu/m/sup 2/ clock and data recovery circuit
Author :
Kaeriyama, S. ; Mizuno, M.
Author_Institution :
NEC, Sagamihara, Japan
Abstract :
A 10Gb/s clock and data recovery circuit for SerDes macro uses half the power and a quarter the die size of prior art. In 0.15/spl mu/m CMOS the CDR dissipates 50mW in an area of 120/spl times/130/spl mu/m/sup 2/ while maintaining a 10Gb/s bandwidth per channel. Jitter tolerance is also improved and the influence of PVT variations is reduced.
Keywords :
CMOS digital integrated circuits; synchronisation; 0.15 micron; 10 Gbit/s; 50 mW; CMOS technology; PVT variations; SerDes macro; clock and data recovery circuit; jitter tolerance; Bandwidth; CMOS technology; Circuits; Clocks; Detectors; Frequency control; Jitter; Signal generators; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234211
