Title :
A second-order semi-digital clock recovery circuit based on injection locking
Author :
Lee, M.-J.E. ; Dally, W.J. ; Poulton, J. ; Greer, T. ; Edmondson, J. ; Farjad-Rad, R. ; Hiok-Tiaq Ng ; Rathi, R. ; Senthinathan, R.
Author_Institution :
Velio Commun., Milpitas, CA, USA
Abstract :
A 3.125Gb/s clock recovery circuit in 0.18/spl mu/m CMOS comprises a multiplying delay-locked loop (MDLL), an injection-locked slave oscillator and a phase control unit. Injection locking reduces MDLL clock distortion and varies the delay of the recovered clock, while a frequency loop in the phase control unit ameliorates the trade off between phase wander and frequency tolerance. Experimental results show high frequency jitter tolerance is improved by 0.08UI.
Keywords :
CMOS digital integrated circuits; delay lock loops; injection locked oscillators; phase control; synchronisation; 0.18 micron; 3.125 Gbit/s; CMOS second-order semi-digital clock recovery circuit; frequency loop; injection-locked slave oscillator; jitter tolerance; multiplying delay-locked loop; phase control unit; Bandwidth; Circuits; Clocks; Delay; Filtering; Filters; Frequency synthesizers; Injection-locked oscillators; Jitter; Master-slave;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234213
