Title :
Tera-scale Computing - Interconnect Challenges
Author_Institution :
Intel - Microprocessor Res., Santa Clara
Abstract :
Future CPU directions are increasingly emphasizing parallel compute platforms which are critically dependent upon upon greater core to core communication and generally stress the overall memory and storage interconnect hierarchy to a much greater degree than extrapolations of past platform needs. Performance is critically dependent upon bandwidth/latency but must be moderated with power and cost considerations. Motivation, requirements, and potential solutions are summarized briefly in this paper.
Keywords :
integrated circuit interconnections; microprocessor chips; parallel processing; core to core communication; interconnect challenges; memory interconnect; parallel compute platforms; storage interconnect; tera-scale computing; Bandwidth; Clocks; Concurrent computing; Integrated circuit interconnections; Microprocessors; Stacking; Testing; Throughput; Tiles; Yarn;
Conference_Titel :
Lasers and Electro-Optics Society, 2007. LEOS 2007. The 20th Annual Meeting of the IEEE
Conference_Location :
Lake Buena Vista, FL
Print_ISBN :
978-1-4244-0925-9
Electronic_ISBN :
1092-8081
DOI :
10.1109/LEOS.2007.4382571
