DocumentCode :
2104791
Title :
A flexible soft IP core for standard implementations of elliptic curve cryptography in hardware
Author :
Ferreira, Bruno F. ; Calazans, Ney L. V.
Author_Institution :
Fac. of Comput. Sci., Pontifical Catholic Univ. of Rio Grande do Sul - PUCRS, Porto Alegre, Brazil
fYear :
2013
fDate :
8-11 Dec. 2013
Firstpage :
577
Lastpage :
580
Abstract :
Elliptic curve cryptography is a rather new, efficient technology for security. However, its implementation is complex and software versions can be prohibitively slow. The main original contribution of this paper is the proposition of a highly parameterizable soft intellectual property core that implements all the operations needed to perform elliptic curve cryptography in hardware. This core supports several standardized elliptic curves. Here, finite field operations use only affine coordinates, which keeps interoperability with software implementations. Also, core operators such as the finite field multiplier and inversion are highly configurable, to enable fulfilling constraints of area or performance, according to what is relevant to each application. The core can thus serve several different purposes, through the setting of parameters that pick the adequate elliptic curve and others that control the finite field multiplier and inversion operator characteristics. Results obtained by synthesizing the core with different parameters for Xilinx FPGAs and 65nm CMOS ASICs show that the exploitable design space is ample: implementations can take from 17 to 5,800μs to execute a point multiplication, taking from 5.7 to 162.2 thousand LUTs in FPGAs or from 16,6 to 360,7 thousand gates in ASICs.
Keywords :
CMOS integrated circuits; application specific integrated circuits; field programmable gate arrays; flexible electronics; microprocessor chips; public key cryptography; CMOS ASICs; Xilinx FPGAs; affine coordinates; elliptic curve cryptography; finite field multiplier; finite field operations; flexible soft IP core; inversion operator characteristics; parameterizable soft intellectual property core; size 65 nm; time 17 mus to 5800 mus; Clocks; Computer architecture; Elliptic curve cryptography; Elliptic curves; Field programmable gate arrays; Galois fields; ASIC; ECC; FPGA; cryptography; soft IP;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location :
Abu Dhabi
Type :
conf
DOI :
10.1109/ICECS.2013.6815480
Filename :
6815480
Link To Document :
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