Fin width scaling criteria of body-tied FinFET in sub-50 nm regime

For better subthreshold swing (SS) and drain induced barrier lowering (DIBL) of FinFETs, the fin width is a more important parameter than the physical gate length. And it should be very thin and fully depleted. In this article, we introduce the fabrication of body-tied FinFETs with various fin widths, fabricated on bulk Si instead of SOI wafer, and propose a new gate length/fin width (L_g/W_fin) criterion to get nearly ideal SS and DIBL for body-tied FinFETs. From experiments and simulations, it is proven that threshold voltage (V_th) control is possible even under a 20 nm narrow fin width, and high performance FinFET operation is obtainable even under a 5 nm fin width.