Title :
A high performance SSL IPSEC protocol aware security processor
Author :
Carlson, D. ; Brasili, D. ; Hughes, A. ; Jain, A. ; Kiszely, T. ; Kodandapani, P. ; Vardharajan, A. ; Xanthopoulos, T. ; Yalala, V.
Author_Institution :
Cavlum Networks, Santa Clara, CA, USA
Abstract :
A 64M transistor security macro processor enables 40k full SSL handshakes per second with 1024 b RSA. The 3DES, AES, ARC4, SHA-1, MD5 and modular exponentiation cryptographic primitives are also supported. The processor is fabricated in a 0.13 /spl mu/m 8M CMOS process and consumes 12 W at 500 MHz.
Keywords :
CMOS digital integrated circuits; cryptography; microprocessor chips; protocols; random number generation; 0.13 micron; 12 W; 500 MHz; 8M CMOS process; ALU; SSL IPSEC protocol aware security processor; cryptographic protocol acceleration; hardwired cryptographic engines; macro-processor; microcode engine; microcode store; modular exponentiation cryptographic primitives; Acceleration; Bandwidth; Cryptographic protocols; Cryptography; Delay; Engines; Entropy; Hardware; Random number generation; Registers;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234240
