Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

Author

Kimura, H. ; Hanyu, T. ; Kameyama, M. ; Fujimori, Y. ; Nakamura, T. ; Takasu, H.

Author_Institution

Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

160

Abstract

Series connection of two ferroelectric capacitors with complementary stored data allows both switching operations and non-destructive storage. This circuitry, used in a fully parallel 32b CAM, results in a dynamic power reduction by 2/3 and static power reduction by 1/9000 compared to a CMOS implementation using 0.6 /spl mu/m ferroelectric CMOS.

Keywords

VLSI; content-addressable storage; ferroelectric capacitors; ferroelectric storage; integrated logic circuits; integrated memory circuits; logic gates; low-power electronics; 0.6 micron; 32 bit; complementary ferroelectric-capacitor logic; complementary stored data; dynamic power reduction; fully parallel CAM; logic-in-memory VLSI; low-power VLSI; nondestructive storage; series connected ferroelectric capacitors; static power reduction; switching operations; Capacitors; Ferroelectric materials; Logic circuits; Logic design; Logic devices; Logic gates; Nonvolatile memory; Research and development; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234248

Filename

1234248