Title :
Timekeeping techniques for predicting and optimizing memory behavior
Author :
Zhigang Hu ; Kaxiras, S. ; Martonosi, M.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Computer architects have long exploited observed memory referencing characteristics to optimize memory performance. We introduce timekeeping metrics for improving program memory performance and power dissipation. Performance and power results for previously proposed timekeeping structures are briefly summarized and implementation options are presented. Simulation focusses on implementation issues.
Keywords :
cache storage; memory architecture; reference circuits; implementation issues; memory behavior; memory referencing characteristics; power dissipation; timekeeping metrics; timekeeping techniques; Application software; Counting circuits; Filtering; Filters; Interleaved codes; Power dissipation; Prefetching; Switches; System performance; Variable structure systems;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234251
