Author :
Taylor, M.B. ; Kim, J. ; Miller, J. ; Wentzlaff, D. ; Ghodrat, F. ; Greenwald, B. ; Hoffman, H. ; Johnson, P. ; Lee, W. ; Saraf, A. ; Shnidman, N. ; Strumpen, V. ; Amarasinghe, S. ; Agarwal, A.
Abstract :
This microprocessor explores an architectural solution to scalability problems in scalar operand networks. The 0.15/spl mu/m 6M process, 331 mm/sup 2/ research prototype issues 16 unique instructions per cycle and uses an on-chip point-to-point scalar operand network to transfer operands among distributed functional units.
Keywords :
microprocessor chips; parallel architectures; pipeline processing; 0.15 micron; distributed functional units; multiple-program-counter microprocessor; point-to-point scalar operand network; scalability problems; Clocks; Computer networks; Delay; Frequency; Microprocessors; Registers; Routing; Silicon; Switches; Tiles;
