DocumentCode
2105486
Title
A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network
Author
Taylor, M.B. ; Kim, J. ; Miller, J. ; Wentzlaff, D. ; Ghodrat, F. ; Greenwald, B. ; Hoffman, H. ; Johnson, P. ; Lee, W. ; Saraf, A. ; Shnidman, N. ; Strumpen, V. ; Amarasinghe, S. ; Agarwal, A.
Author_Institution
MIT, Cambridge, MA, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
170
Abstract
This microprocessor explores an architectural solution to scalability problems in scalar operand networks. The 0.15/spl mu/m 6M process, 331 mm/sup 2/ research prototype issues 16 unique instructions per cycle and uses an on-chip point-to-point scalar operand network to transfer operands among distributed functional units.
Keywords
microprocessor chips; parallel architectures; pipeline processing; 0.15 micron; distributed functional units; multiple-program-counter microprocessor; point-to-point scalar operand network; scalability problems; Clocks; Computer networks; Delay; Frequency; Microprocessors; Registers; Routing; Silicon; Switches; Tiles;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234253
Filename
1234253
Link To Document