Title :
A 30Gb/s 1:4 demultiplexer in 0.12/spl mu/m CMOS
Author :
Rylyakov, A. ; Rylov, S. ; Ainspan, H. ; Gowda, S.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
A 1:4 demultiplexer, implemented in 0.12/spl mu/m SOI and bulk CMOS technology, operates with a BER below 10/sup -13/ at 30Gb/s (SOI) and 26Gb/s (bulk) input data rates (2/sup 7/-1 PRBS), drawing 200mA from a 2V supply. At 1.2V, the chips draw 100mA and operates at input data rates of 21Gb/s (SOI) and 18Gb/s (bulk). The design has an active area of 300/spl mu/m /spl times/ 90/spl mu/m.
Keywords :
CMOS digital integrated circuits; demultiplexing equipment; silicon-on-insulator; 0.12 micron; 1.2 V; 100 mA; 1:4 demultiplexer; 2 V; 200 mA; 21 Gbit/s; 30 Gbit/s; BER; CMOS; SOI; Si; active area; bulk CMOS technology; input data rates; Binary trees; CMOS digital integrated circuits; CMOS technology; Clocks; Demultiplexing; Frequency conversion; Latches; Multiplexing; Testing; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234255
