A 2.5 to 10GHz clock multiplier unit with 0.22ps RMS jitter in a 0.18/spl mu/m CMOS technology

Author

van de Beek, R.C.H. ; Vaucher, C.S. ; Leenaerts, D.M.W. ; Pavlovic, N. ; Mistry, K. ; Klumperink, E.A.M. ; Nauta, B.

Author_Institution

IC-Design Group, Twente Univ., Enschede, Netherlands

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

178

Abstract

A fully integrated clock multiplier unit uses 100mW to generate a 10GHz output clock with 0.22ps RMS jitter, exceeding the SONET OC-192 jitter generation specifications. An LC VCO is controlled by a PLL employing a fast linear phase detector in combination with a frequency detector, both running at 2.5GHz. The jitter and power dissipation are lower than that of previous CMOS implementations.

Keywords

CMOS digital integrated circuits; clocks; digital phase locked loops; frequency multipliers; jitter; low-power electronics; phase detectors; 0.18 micron; 100 mW; 2.5 to 10 GHz; CMOS technology; PLL; RMS jitter; SONET OC-192 jitter generation specifications; clock multiplier unit; fast linear phase detector; frequency detector; jitter; power dissipation; CMOS technology; Circuits; Clocks; Frequency conversion; Jitter; Optical transmitters; Phase detection; Phase frequency detector; Signal generators; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234256

Filename

1234256