DocumentCode
2105616
Title
Accurate subthreshold leakage model for nanoscale MOSFET transistor
Author
Rjoub, Abdoul ; Al-Taradeh, Nedal R. ; Al-Mistarihi, Mamoun F.
Author_Institution
Comput. Eng. Dept., Jordan Univ. of Sci. & Technol., Irbid, Jordan
fYear
2013
fDate
8-11 Dec. 2013
Firstpage
711
Lastpage
714
Abstract
In this paper, a new accurate and efficient model for subthreshold leakage current is proposed for nanoscale metal oxide semiconductor field effect transistor (MOSFET). The influence of drain induced barrier lowering (DIBL) and gate induced drain lowering (GIDL) due to short channel effect (SCE) on subthreshold leakage is modeled and included in the characteristic equation. The linearization factor (Υ) and subthreshold swing coefficient (γ) are modeled and included to make the proposed model faster than the recent published models. The evaluation of the proposed model shows very good agreement when compared with simulation results of BSIM4 Level 54 Model using HSPICE tool.
Keywords
MOSFET; nanoelectronics; semiconductor device models; BSIM4 Level 54 Model; HSPICE tool; accurate subthreshold leakage model; drain induced barrier lowering; gate induced drain lowering; linearization factor; nanoscale MOSFET transistor; nanoscale metal oxide semiconductor field effect transistor; short channel effect; subthreshold leakage current; subthreshold swing coefficient; Logic gates; MOSFET; Mathematical model; Nanoscale devices; Semiconductor device modeling; Semiconductor process modeling; Subthreshold current; (γ) Metal Oxide Semiconductor Field Effect Transistor (MOSFET); Drain Induced Barrier Lowering (DIBL); Gate Induced Drain Lowering (GIDL); Short Channel Effect (SCE); Sub threshold leakage (Isub ); linearization factor;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on
Conference_Location
Abu Dhabi
Type
conf
DOI
10.1109/ICECS.2013.6815513
Filename
6815513
Link To Document