Variability analysis of a 28nm near-threshold synchronous voltage converter

An important synchronous circuit element in low-power digital circuit design is the voltage level shifter at the boundary between voltage domains. In this paper, we present a full variability analysis of an optimized, synchronous pulsed half-latch level converter (PHLC) in the GLOBALFOUNDRIES 28nm technology. The variability analysis clearly illustrates the impact of ultra-low-power design on delay, energy and the energy-delay product (EDP). In particular, the normalized standard deviation for EDP in near-threshold operation is more than twice its value for nominal-supply operation. The analysis also illustrates the impact of variability on the architectural and topological decisions a designer has to make in ultra-low power design.