Hardware implementation of IIR digital filters for programmable devices

This paper presents a methodology for implementing infinite impulse response (IIR) filters in hardware. The methodology we explore utilizes concepts inherent to both second order sections (SOS) and state-space models. We illustrate an improvement of several orders of magnitude in computational accuracy using the state-space SOS IIR filters over the cascade designs. Additionally, the state-space hardware model exhibits a shorter critical path when mapped onto a programmable device. We compare the performance of the state-space hardware model to conventional IIR filter implementations using a Spartan 3 XC3S400-4FG320 FPGA to illustrate the merits of this work.