DocumentCode
2106296
Title
A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology
Author
Lee, J. ; Razavi, B.
Author_Institution
California Univ., Los Angeles, CA, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
242
Abstract
A 40-Gb/s clock recovery circuit incorporates a quarter-rate phase detector and a multiphase LC oscillator to retime the data and demultiplex it into four 10 Gb/s outputs. Fabricated in 0.18 /spl mu/m CMOS technology, the circuit produces a clock jitter of 0.9 ps RMS and 9.67 ps peak-to-peak while consuming 144 mW.
Keywords
CMOS integrated circuits; application specific integrated circuits; digital communication; high-speed integrated circuits; optical communication equipment; synchronisation; 0.18 micron; 10 Gbit/s; 144 mW; 40 Gbit/s; CMOS technology; clock jitter; clock/data recovery circuit; demultiplexing; multiphase LC oscillator; quarter-rate phase detector; CMOS technology; Circuits; Clocks; Inductors; Phase detection; Phase noise; Power transmission lines; Sampling methods; Voltage; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234285
Filename
1234285
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