A 1.3 GHz fifth generation SPARC64 microprocessor

Author

Ando, H. ; Yoshida, Y. ; Inoue, A. ; Sugiyama, I. ; Asakawa, T. ; Morita, K. ; Muta, T. ; Motokurumada, T. ; Okada, S. ; Yamashita, H. ; Satsukawa, Y. ; Konmoto, A. ; Yamashita, R. ; Sugiyama, H.

Author_Institution

Fujitsu, Kawasaki, Japan

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

246

Abstract

A fifth generation SPARC64 processor implemented in 130 nm CMOS process with 8 layers of Cu metallization operates with a 1.3 GHz clock and dissipates 34.7 W. The processor is a 4-issue out-of-order design with 2 MB on-chip level-2 cache. Error checking is added on the data-path in addition to memory. An instruction is retried for correction when an error is detected in the datapath.

Keywords

CMOS digital integrated circuits; VLSI; copper; error detection; fifth generation systems; high-speed integrated circuits; integrated circuit metallisation; microprocessor chips; pipeline processing; silicon-on-insulator; 1.3 GHz; 130 nm; 2 MB; 34.7 W; 4-issue out-of-order design; CMOS SOI process; Cu; Cu metallization; data-path error checking; fifth generation SPARC64 microprocessor; on-chip level-2 cache; pipeline stages; superscalar design; Bandwidth; CMOS process; Circuits; Clocks; Delay; Latches; Microprocessors; Noise generators; Pipelines; Protection;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234286

Filename

1234286