A VLIW processor with reconfigurable instruction set for embedded applications

Author

Campi, F. ; Toma, M. ; Lodi, A. ; Cappelli, A. ; Canegallo, R. ; Guerrieri, R.

Author_Institution

ARCES, Bologna Univ., Italy

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

250

Abstract

A RISC VLIW processor implements dynamic instruction set extension integrating a pipelined, run-time reconfigurable datapath. A 0.18 /spl mu/m 6M CMOS chip prototype achieves energy consumption reduction up to 90% and time reduction of 13/spl times/ on a signal processing algorithm benchmark. The IC contains 12M transistors and dissipates 120 mW at 80 MHz from a 1.8 V supply.

Keywords

CMOS digital integrated circuits; VLSI; embedded systems; instruction sets; microprocessor chips; parallel architectures; pipeline processing; reconfigurable architectures; 0.18 micron; 1.8 V; 120 mW; 80 MHz; CMOS chip; RISC VLIW processor; dynamic instruction set extension; embedded applications; energy consumption reduction; pipelined run-time reconfigurable datapath; reconfigurable instruction set; signal processing algorithm benchmark; time reduction; Electronics packaging; Hardware; High level languages; Logic programming; Pipelines; Programmable logic arrays; Programmable logic devices; Reconfigurable logic; Runtime; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234288

Filename

1234288