Author :
Kaneko, S. ; Sawai, K. ; Masui, N. ; Ishimi, K. ; Itou, T. ; Satou, M. ; Kondo, H. ; Okumura, N. ; Takata, Y. ; Takata, H. ; Sakugawa, M. ; Higuchi, T. ; Ohtani, S. ; Sakamoto, K. ; Ishikawa, N. ; Nakajima, M. ; Iwata, S. ; Hayase, K. ; Nakano, S. ; Nakaz
Abstract :
This 600 MHz single-chip multiprocessor consists of two M32R 32 b CPU cores and 512 kB shared SRAM and is designed for embedded systems. Embedded processors are required with increased performance while power dissipation is paramount for battery-operated applications. The design is implemented in a single-chip in a 0.15 /spl mu/m 4M CMOS process and operates at 600 MHz with 800 mW peak power dissipation.
Keywords :
CMOS digital integrated circuits; VLSI; embedded systems; high-speed integrated circuits; microprocessor chips; pipeline processing; random-access storage; shared memory systems; 0.15 micron; 32 bit; 4.8 GB/s; 4M CMOS process; 512 kB; 600 MHz; 800 mW; M32R CPU cores; battery-operated applications; embedded systems; internal shared pipelined bus; shared SRAM; shared internal memory; single-chip multiprocessor; Cache memory; Delay; Energy consumption; Microcontrollers; Pipelines; Power dissipation; Random access memory; Registers; System-on-a-chip; Technical Activities Guide -TAG;
