Synthesizable assertion checkers in high levels of abstraction

Verification is a challenge that consumes an increasing part of the design time in the design flow of modern hardware systems. We propose an Assertion Based Verification (ABV) method with embedding synthesizable clock-accurate assertion checkers in higher levels of abstraction in the design flow. Both the Design Under Verification (DUV) and its synthesizable assertion checkers are described using the same language which leads to an easier integration of the checkers. Using this approach on a case study confirms its feasibility without any penalty in the working frequency with less than 5% increased area consumption on a Kintex7 FPGA.