Author :
Shiratake, S. ; Miyakawa, T. ; Takeuchi, Y. ; Ogiwara, R. ; Kamoshida, M. ; Hoya, K. ; Oikawa, K. ; Ozaki, T. ; Kunishima, I. ; Yamakawa, K. ; Sugimoto, S. ; Takashima, D. ; Joachim, H.O. ; Rehm, N. ; Wohlfahrt, J. ; Nagel, N. ; Beitel, G. ; Jacob, M. ; R
Abstract :
A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.
Keywords :
CMOS memory circuits; ferroelectric storage; random-access storage; 0.20 micron; 3 muA; 32 Mbit; 65.6 percent; CMOS chip; chain FeRAM; nonvolatile memory cell; segment/stitch array architecture; stacked capacitor technology; CMOS technology; Capacitors; Circuits; Delay; Ferroelectric films; Nonvolatile memory; Protection; Random access memory; Voltage; Wiring;
