DocumentCode
2106708
Title
A 32Mb chain FeRAM with segment/stitch array architecture
Author
Shiratake, S. ; Miyakawa, T. ; Takeuchi, Y. ; Ogiwara, R. ; Kamoshida, M. ; Hoya, K. ; Oikawa, K. ; Ozaki, T. ; Kunishima, I. ; Yamakawa, K. ; Sugimoto, S. ; Takashima, D. ; Joachim, H.O. ; Rehm, N. ; Wohlfahrt, J. ; Nagel, N. ; Beitel, G. ; Jacob, M. ; R
Author_Institution
Toshiba, Yokohama, Japan
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
282
Abstract
A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.
Keywords
CMOS memory circuits; ferroelectric storage; random-access storage; 0.20 micron; 3 muA; 32 Mbit; 65.6 percent; CMOS chip; chain FeRAM; nonvolatile memory cell; segment/stitch array architecture; stacked capacitor technology; CMOS technology; Capacitors; Circuits; Delay; Ferroelectric films; Nonvolatile memory; Protection; Random access memory; Voltage; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234302
Filename
1234302
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