Title :
512 Mb PROM with 8 layers of antifuse/diode cells
Author :
Crowley, M. ; Al-Shamma, A. ; Bosch, D. ; Farmwald, M. ; Fasoli, L. ; Ilkbahar, A. ; Johnson, M. ; Kleveland, B. ; Lee, T. ; Tz-yi Liu ; Quang Nguyen ; Scheuerlein, R. ; So, K. ; Thorp, T.
Author_Institution :
Matrix Semicond., Santa Clara, CA, USA
Abstract :
A 3.3 V, 512 Mb PROM uses a transistorless memory cell containing an antifuse and diode. A bit area of 1.4F/sup 2/ including all overhead is achieved by stacking cells 8 high above the 0.25 /spl mu/m CMOS substrate. Read bandwidth is 1 MB/s and write bandwidth is 0.5 MB/s. A 72 b Hamming code provides fault tolerance.
Keywords :
CMOS memory circuits; PROM; error correction codes; fault tolerant computing; 0.25 micron; 0.5 MB/s; 1 MB/s; 3.3 V; 512 Mbit; 72 bit; CMOS substrate; Hamming code; PROM; antifuse/diode cells; fault tolerance; stacked cells; transistorless memory cell; Anodes; Cathodes; Circuits; Decoding; Noise cancellation; Operational amplifiers; PROM; Semiconductor devices; Semiconductor diodes; Semiconductor materials;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234303
