A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

Author

Elmhurst, D. ; Bains, Robert ; Bressie, T. ; Bueb, C. ; Carrieri, E. ; Chauhan, B. ; Chrisman, Nicholas ; Dayley, M. ; De Luna, R. ; Fan, Kuikui ; Goldman, M. ; Govindu, P. ; Huq, A. ; Khandaker, Muhammad ; Kreifels, J. ; Krishnamachari, S. ; Lavapie, P.

Author_Institution

Intel, Folsom, CA, USA

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

286

Abstract

A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.

Keywords

CMOS memory circuits; flash memories; high-speed integrated circuits; 0.13 micron; 1.8 V; 125 MHz; 128 Mbit; 55 ns; CMOS NOR process technology; erase operation; flexible multi-partition memory architecture; flexible read while write; multi-level cell flash memory; program operation; synchronous operation; Capacitance; Circuits; Costs; Diodes; Flash memory; Lithography; Memory architecture; Nonvolatile memory; Silicon compounds; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234304

Filename

1234304