Title :
16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors
Author :
Osada, K. ; Saitoh, Y. ; Ibe, E. ; Ishibashi, K.
Author_Institution :
Central Res. Lab., Hitachi, Tokyo, Japan
Abstract :
A 16 Mb SRAM based on an electric-field-relaxed scheme and an alternate error checking and correction architecture for handling cosmic-ray-induced multi-errors is realized in 0.13 /spl mu/m CMOS technology. The IC has a 16.7 fA/cell standby current, a cell size of 2.06 /spl mu/m/sup 2/ and a 99.5% smaller SER.
Keywords :
CMOS memory circuits; SRAM chips; cosmic ray interactions; error correction; leakage currents; radiation hardening (electronics); 0.13 /spl mu/m CMOS technology; 0.13 micron; 16 Mbit; 16.7 fA; 16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM; SER; alternate error checking and correction architecture; cell size; cosmic-ray-induced multi-errors; electric-field-relaxed scheme; standby current; Circuits; Error correction; Error correction codes; Laboratories; Leakage current; MOS devices; MOSFETs; Random access memory; Subthreshold current; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234308
