Title :
A 1.0 V 256 Mb SDRAM with offset-compensated direct sensing and charge-recycled precharge schemes
Author :
Sim, J.Y. ; Kwon, K.W. ; Choi, J.H. ; Lee, S.H. ; Kim, D.M. ; Hwang, H.R. ; Chun, K.C. ; Seo, Y.H. ; Hwang, H.S. ; Seo, D.I. ; Kim, C. ; Cho, S.I.
Author_Institution :
Memory Div., Samsung Electron., Hwasung, South Korea
Abstract :
A 1.0 V, 256 Mb SDRAM is designed in a 0.1 /spl mu/m CMOS technology. For low voltage applications, an offset compensated direct current sensing scheme improves refresh time as well as sensing performance. A charge-recycled precharge reuses the word-line discharge current to generate the boosted voltage required for equalization without charge pumping. At 1.0 V, the access time is 25 ns and the current is 15 mA.
Keywords :
CMOS memory circuits; SRAM chips; compensation; 0.1 micron; 1.0 V; 15 mA; 25 ns; 256 Mbit; CMOS technology; SDRAM; charge-recycled precharge scheme; direct sensing scheme; equalization; low voltage applications; offset compensation; refresh time; sensing performance; word-line discharge current; Consumer electronics; Delay; Differential amplifiers; Low voltage; Operational amplifiers; Random access memory; SDRAM; Switches; Switching circuits; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234312
