DocumentCode
2106995
Title
A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM with on-die termination and off-chip driver calibration
Author
Yoo, C. ; Kyung, K. ; Han, G.-H. ; Lim, K. ; Lee, H. ; Chai, J. ; Heo, N.-W. ; Byun, G. ; Lee, D.-J. ; Choi, H.-I. ; Choi, H.-C. ; Kim, C.-H. ; Cho, S.
Author_Institution
Samsung Electron., Hwasung, South Korea
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
312
Abstract
A 1.8 V 700 Mb/s/pin 512 Mb DDR-II SDRAM is JEDEC standard compliant. With the hierarchical I/O line and local sensing, t/sub AA/ /t/sub RCD//t/sub RP/ of 3/3/3 at 533 Mb/s are achieved in the design. For signal integrity at 533 Mb/s, off-chip driver calibration and on-die termination are employed.
Keywords
CMOS memory circuits; SRAM chips; calibration; high-speed integrated circuits; 1.8 V; 512 Mbit; 533 Mbit/s; 700 Mbit/s; DDR-II SDRAM; JEDEC standard compliant; hierarchical I/O line sensing; local sensing; off-chip driver calibration; on-die termination; Bonding; Calibration; Delay; Driver circuits; Low voltage; Multiplexing; Prefetching; Random access memory; SDRAM; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234313
Filename
1234313
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