A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

Author

Ho Young Song ; Seong Jin Jang ; Jin Seok Kwak ; Cheol Su Kim ; Chang Man Kang ; Dae Hyun Jeong ; Yun Sik Park ; Min Sang Park ; Kyoung Su Byun ; Woo Jin Lee ; Young Cheol Cho ; Won Hwa Shin ; Young Uk Jang ; Seok Won Hwang ; Young Hyun Jun ; Soo In Cho

Author_Institution

Samsung Electron., Hwasung, South Korea

fYear

2003

fDate

13-13 Feb. 2003

Firstpage

314

Abstract

For operating frequencies exceeding 500 MHz, the timing margin of the I/O interface is critical and requires the data input-output timing accuracy to be within 200 ps. To meet the requirement, the designed SDRAM adopts a digitally self-calibrated on-die-termination with linearity error of /spl plusmn/1% and achieves over 1.2 Gbps/pin stable operation by using window matching and latency control. The chip is fabricated in a 0.13 /spl mu/m triple-well DRAM process.

Keywords

CMOS memory circuits; SRAM chips; circuit stability; high-speed integrated circuits; timing; 0.13 micron; 1.2 Gbit/s; 500 MHz; I/O interface; data input-output timing accuracy; digitally self-calibrated termination; double data rate SDRAM; high speed DDR SDRAM; latency control; on-die-termination; stable operation; triple-well DRAM process; window matching; Circuits; Clocks; DRAM chips; Frequency; Linearity; Random access memory; Resistors; SDRAM; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-7707-9

Type

conf

DOI

10.1109/ISSCC.2003.1234314

Filename

1234314