DocumentCode
2107138
Title
A 69 mW 10 b 80 MS/s pipelined CMOS ADC
Author
Byung-Moo Min ; Kim, P. ; Boisvert, D. ; Aude, A.
Author_Institution
Nat. Semicond., Salem, NH, USA
fYear
2003
fDate
13-13 Feb. 2003
Firstpage
324
Abstract
A 10 b 80 MHz pipelined ADC with an active area of 1.85 mm/sup 2/ is realized in a 0.18 /spl mu/m dual gate oxidation CMOS process and achieves 72.8 dBc SFDR, 57.92 dB SNR, and 9.29 ENOB for a 100 MHz input at full sampling rate. The ADC shares an amplifier between two successive pipeline stages in order to achieve a power consumption of 69 mW at 3 V.
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; pipeline processing; signal sampling; switched capacitor networks; 0.18 micron; 10 b 80 MHz pipelined ADC; 10 bit; 3 V; 69 mW; 80 MHz; CMOS ADC; ENOB; SFDR; SNR; active area; amplifier sharing; full sampling rate; power consumption; successive pipeline stages; Bandwidth; Broadband amplifiers; Capacitors; Clocks; Energy consumption; Operational amplifiers; Pipelines; Power amplifiers; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-7707-9
Type
conf
DOI
10.1109/ISSCC.2003.1234318
Filename
1234318
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