Title :
A 12 b 75 MS/s pipelined ADC using open-loop residue amplification
Author :
Murmann, B. ; Boser, B.E.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
The multi-bit first stage of a 12 b 75 MS/s pipelined ADC uses an open-loop gain stage to achieve more than 60% residue amplifier power savings over a conventional implementation. Statistical background calibration removes linear and nonlinear residue errors in the digital domain. The prototype IC achieves 68.2 dB SNR, -76 dB THD, occupies 7.9 mm/sup 2/ in 0.35 /spl mu/m CMOS and consumes 290 mW at 3 V.
Keywords :
CMOS integrated circuits; analogue-digital conversion; harmonic distortion; low-power electronics; pipeline processing; 0.35 /spl mu/m CMOS; 0.35 micron; 12 b 75 MS/s pipelined ADC; 12 bit; 290 mW; 3 V; SNR; THD; digital domain; linear residue errors; multi-bit first stage; nonlinear residue errors; open-loop gain stage; open-loop residue amplification; power consumption; residue amplifier power savings; statistical background calibration; Bandwidth; Calibration; Error correction; Feedback; Gain; High power amplifiers; Low-noise amplifiers; Pipelines; Power amplifiers; Power dissipation;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234320
