Title :
A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS
Author :
Vangal, S. ; Hoskote, Y. ; Somasekhar, D. ; Erraguntla, V. ; Howard, J. ; Ruhl, G. ; Veeramachaneni, V. ; Finan, D. ; Mathew, S. ; Borkar, N.
Author_Institution :
Microprocessor Res. Labs., Intel, Hillsboro, OR, USA
Abstract :
A 32 b single-cycle floating point accumulator that uses base 32 and carry-save format with delayed addition is described. Combined algorithmic, logic and circuit techniques enable multiply-accumulate operation at 5 GHz. In a 90 nm 7M dual-V/sub T/ CMOS process, the 2 mm/sup 2/ prototype contains 230K transistors and dissipates 1.2 W at 5 GHz, 1.2 V and 25/spl deg/C.
Keywords :
CMOS logic circuits; carry logic; floating point arithmetic; logic design; multiplying circuits; 1.2 V; 1.2 W; 25 degC; 32 bit; 5 GHz; 5 GHz floating point multiply-accumulator; 90 nm; 90 nm dual V/sub T/ CMOS; algorithmic techniques; base 32 format; carry-save format; circuit techniques; delayed addition; logic techniques; power dissipation; single-cycle floating point accumulator; Acceleration; Added delay; Adders; Circuits; Logic arrays; Microprocessors; Mirrors; Output feedback; Pipeline processing; Signal generators;
Conference_Titel :
Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7707-9
DOI :
10.1109/ISSCC.2003.1234322
